STPCCLIENT datasheet(12/48 Pages) STMICROELECTRONICS

12 / 48 page

PIN DESCRIPTION

12/48

Issue 1.7 - February 8, 2000

Table 2-2. Definition of Signal Pins

Signal Name

Dir

Description

Qty

BASIC CLOCKS RESETS & XTAL

SYSRSTI#

System Reset / Power good

SYSRSTO#*

Reset Output to System

XTALI

14.3MHz External Oscillator Input

XTALO

I/O

14.3MHz External Oscillator Input

PCI_CLKI

33MHz PCI Input Clock

PCI_CLKO

33MHz PCI Output Clock (from internal PLL)

ISA_CLK

ISA Clock Output - Multiplexer Select Line For IPC

ISA_CLK2X

ISA Clock x 2 Output - Multiplexer Select Line For IPC

OSC14M*

ISA bus synchronisation clock

HCLK*

Host Clock (Test)

DEV_CLK

24MHz Peripheral Clock (floppy drive)

GCLK2X*

I/O

80MHz Graphics Clock

DCLK*

I/O

135MHz Dot Clock

DCLK _DIR*

Dot Clock Direction

VDD_xxx_PLL

Power Supply for PLL Clocks

MEMORY INTERFACE

MA[11:0]*

I/O

Memory Address

RAS#[3:0]

Row Address Strobe

CAS#[7:0]

Column Address Strobe

MWE#

Write Enable

MD[63:0]*

I/O

Memory Data

PCI INTERFACE

AD[31:0]*

I/O

PCI Address / Data

CBE[3:0]*

I/O

Bus Commands / Byte Enables

FRAME#*

I/O

Cycle Frame

TRDY#*

I/O

Target Ready

IRDY#*

I/O

Initiator Ready

STOP#*

I/O

Stop Transaction

DEVSEL#*

I/O

Device Select

PAR*

I/O

Parity Signal Transactions

SERR#*

System Error

LOCK#

PCI Lock

PCI_REQ#[2:0]*

PCI Request

PCI_GNT#[2:0]*

PCI Grant

PCI_INT[3:0]*

PCI Interrupt Request

VDD5

5V Power Supply for PCI ESD protection

ISA AND IDE COMBINED ADDRESS/DATA

LA[23:22]*/ SCS3#,SCS1#

I/O

Unlatched Address (ISA) / Secondary Chip Select (IDE)

LA[21:20]*/ PCS3#,PCS1#

I/O

Unlatched Address (ISA) / Primary Chip Select (IDE)

LA[19:17]*/ DA[2:0]

Unlatched Address (ISA) / Address (IDE)

RMRTCCS#* / DD[15]

I/O

ROM/RTC Chip Select / Data Bus bit 15 (IDE)

KBCS#* / DD[14]

I/O

Keyboard Chip Select / Data Bus bit 14 (IDE)

Note; * denotes theat the pin is V5T (see Section 4. )

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