STW4811MBRATSLASHLF datasheet(74/86 Pages) STMICROELECTRONICS

tên linh kiện	STW4811MBRAT/LF

Giải thích chi tiết về linh kiện	Power management for multimedia processors

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74 / 86 page

STw4811M/STw4811N

Electrical and timing characteristics

73/85

5.6

SD/MMC/SDIO card interface

Settling time

OFF->ON

IOUT = 0mA

µs

Discharge time

ON>OFF

IOUT = 0mA

400

µs

From 4.8 V to 5.5 V, charge pump is “Off” and no OTG feature is provided

Guaranteed by design

Table 51.

USB OTG transceiver (continued)

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

Table 52.

SD/MMC/SDIO card interface

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

VMMC regulator specifications (’pdn_vmmc’ = 1)

VIN

Input voltage

VOUT = 3.3 V

VOUT = 3 V

VOUT = 2.85 V

VOUT = 2.7 V

VOUT = 2.6 V

VOUT = 1.8/1.85 V

3.55

3.25

3.1

2.95

2.85

2.7

3.6

5.5

VOUT

Output voltage

-3%

3.3

2.85

2.7

2.6

1.85

1.8

+3%

IOUT

Output current

150

ISHORT

Short circuit

current limitation

240

360

600

Quiescent current

IOUT = 0 mA

µA

ILKG

Power-down

current

’pdn_vmmc’ = 0

µA

PSRR(1)

Power supply

rejection

IOUT = 150 mA

Vpp = 0.3 V

f < 20 kHz

LIR

(1)

Line regulation

VOUT=2.85 V

VBAT: [3.1; 4.8]V

5mV

LDR

(1)

Load regulation

VOUT=2.85 V

IOUT= [1; 150] mA

LIRT

Transient line

regulation

VOUT=2.85 V

VBAT: 3.1 to 3.4V

tR = tF = 10 µs.

2mV

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