Data bus configuration

STV7733

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Data bus configuration

Below, Table 2 describes the position of the first data sampled by the first rising edge of the

SCLK clock. For the first configuration described in Table 2, that is, with input DIR = “H”,

output OUT1. After 80 clock pulses, data on OUT1 will be shifted to OUT317 - on the

high-to-low transition of input /DL. Input /CS is the chip select.

Note:

Data is transferred from the shift register to a latch block and then on to power output stages

on the falling edge of input /DL, see Figure 2.

All output data is stored and held in the latch block on the rising edge of the input /DL, see

Figure 2.

Table 2.

Data bus configuration

/CS

DIR

Input

Position

SCLK pulse number

Comment

OUT1

OUT2

…

OUT79

OUT80

L

H

OUT

OUT

OUT

OUT

01

02

03

04

05

06

07

08

313

314

315

316

317

318

319

320

Left/Right shift

L

L

OUT

OUT

OUT

OUT

320

319

318

317

316

315

314

313

08

07

06

05

04

03

02

01

Right/Left shift