Additional memory devices

STn8810S12

12/16

3.2

DDR mobile RAM device

The 512-Mbit DDR mobile RAM is organized as 8,388,608 × 16 bits × 4 banks. It achieves

low power consumption and high-speed data transfer using a 2-bit prefetch pipeline

architecture.

Command and address inputs are synchronized with the positive edge of the clock. Data

inputs and outputs are synchronized with both edges of DQS (data strobe). DLL is not

implemented.

The device architecture is illustrated in

Figure 5.

Figure 5.

DDR mobile RAM architecture

3.3

External memory support

●

One chip-select available for external NAND Flash connection.

Bank 3

Bank 2

Bank 1

Command

decoder

Control

logic

Memory cell

array

Column decoder

Sense amplifier

Bank 0

Row

address

buffer

and

refresh

counter

Column

address

buffer

and

burst

counter

Data control circuit

Latch circuit

Input and output

buffer

/CS

/RAS

/CAS

/WE

Mode

register

CK

/CK

CKE

DQS

DM

DQ

Clock

generator