Data Brief

For further information contact your local STMicroelectronics sales office.

April 2007

Rev 2

1/5

5

STLS2E02

Loongson 2E:

700MHz 64-bit superscalar MIPS® based microprocessor

Features

support (SIMD)

chip 512KB unified L2 cache

– 4W @ 700MHz

Description

The STLS2E02, is a MIPS based 64-bit

superscalar microprocessor, able to issue four

instructions per clock cycle among six functional

units: two integer, two single/double-precision

floating-point, one 64bit SIMD and one load/store

unit.

The microarchitecture is organized with nine

stages of pipeline and support of dynamic branch

prediction.

The memory hierarchy is composed by the first

level of 64KB 4-way set associative cache for

instructions and data, the second level of 512KB

unified 4-ways set associative cache and the

Memory Management Unit with Table Lookside

Buffer.

The Loongson microprocessor family is the

outcome of a successful collaboration started in

2004 between STMicroelectronics and the

Institute of Computing Technology, part of the

Chinese Academy of Science. Loongson

microprocessors were co-developed by

STMicroelectronics and the Institute of

Computing Technology to address all the

applications requiring high level of performance

and low power dissipation.

PBGA452

Table 1.

Device summary

Part numbers

Package

Packing

STLS2E02

PBGA452 (35x35x2.33mm)

Tray

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