SPEAR-09-B042 datasheet(46/66 Pages) STMICROELECTRONICS

tên linh kiện	SPEAR-09-B042

Giải thích chi tiết về linh kiện	SPEAr짰 BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC

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Standard customization

SPEAR-09-B042

46/66

The following pre-defined shapes are available:

●

short frame narrow-band delayed and non delayed

●

short frame wide-band delayed and non delayed

●

I2S or serial aligned long frame.

Figure 9.

Pre-defined frame sync shapes (slave or master)

SYN4 to SYNC7 are generated from the sync memory. The sync memory has 1024 words

per four bytes. Byte0 of each location is used to generate SYNC4. Byte1 for SYNC5, Byte2

for SYNC6 and Byte3 for SYNC7. The MSB of each byte is issued first. The LSB is issued

the last. This covers the 1024 possible time slots for the four sync signals.

TDM timeslot switching

Any of the output time slots can receive any input timeslot of the previous frame. The

connection memory is part of the action memory, informing which timeslot has to be output.

The data memory contains two banks. One storing the actual frame from the DIN pin (if

switching has been validated for this timeslot in the action memory), the other outputting the

data from the previous frame on DOUT (if the switching has been validated and high

impedance bit is not set in the action memory).

The delay between out_TSy receiving IN_TSx for a TDM containing N+1 timeslots is

constant:

Delay(TS)= y + (N+1- x)

with x and y between 0 and N.

Figure 10 shows an example with N+1 = 32.

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