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STA559BWQS bảng dữ liệu(PDF) 37 Page - STMicroelectronics

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STA559BWQS bảng dữ liệu(HTML) 37 Page - STMicroelectronics

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STA559BWQS
Register description
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5.5
Configuration register E (addr 0x04)
5.5.1
Max power correction variable
Table 36.
Max power correction variable
5.5.2
Max power correction
Table 37.
Max power correction
Setting the MPC bit turns on special processing that corrects the STA50x power device at
high power. This mode should lower the THD + N of a full DDX system at maximum power
output and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-
out channels.
5.5.3
Noise-shaper bandwidth selection
Table 38.
Noise-shaper bandwidth selection
D7
D6
D5
D4
D3
D2
D1
D0
SVE
ZCE
DCCV
PWMS
AME
NSBW
MPC
MPCV
11
0
0
0
0
1
0
Bit
RW
RST
Name
Description
0RW
0
MPCV
Max power correction variable:
0: Use standard MPC coefficient
1: Use MPCC bits for MPC coefficient
Bit
RW
RST
Name
Description
1RW
1
MPC
Max power correction: setting of 1 enables power
bridge correction for THD reduction near maximum
power output.
Bit
RW
RST
Name
Description
2
RW
0
NSBW
Noise-shaper bandwidth selection:
1 - 3rd order NS
0 - 4th order NS



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