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LFXP bảng dữ liệu(PDF) 11 Page - Lattice Semiconductor

tên linh kiện LFXP
Giải thích chi tiết về linh kiện  LatticeXP Family Data Sheet
PDF  130 Pages
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nhà sản xuất  LATTICE [Lattice Semiconductor]
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LFXP bảng dữ liệu(HTML) 11 Page - Lattice Semiconductor

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2-8
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-6. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
From Routing
From Routing
From
Routing
From
Routing
From
Routing
Clock
Input
Clock
Input
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS2
DCS2
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.



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