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63 / 159 page  ST7LITE1xB 63/159 DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.4 Output Compare Mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and DCRxL reg- isters, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set. In single Timer mode the output compare function is performed only on CNTR1. The difference be- tween both the modes is that, in Single Timer mode, CNTR1 can be compared with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0 or DCR1 and CNTR2 is compared with DCR2 or DCR3. Notes: 1. The output compare function is only available for DCRx values other than 0 (reset value). 2. Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle Registers and these values are transferred in Active Duty Cycle Registers after an overflow event if the corre- sponding transfer bit (TRANx bit) is set. Output compare is done by comparing these active DCRx values with the counters. Figure 42. Block Diagram of Output Compare Mode (single timer) DCRx OUTPUT COMPARE CIRCUIT COUNTER 1 (ATCSR) CMPIE PRELOAD DUTY CYCLE REG0/1/2/3 ACTIVE DUTY CYCLE REGx CNTR1 TRAN1 (ATCSR2) OVF (ATCSR) CMPFx (PWMxCSR) CMP REQUEST INTERRUPT 1 |
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