PM6681ATR datasheet(36/47 Pages) STMICROELECTRONICS

tên linh kiện	PM6681ATR

Giải thích chi tiết về linh kiện	Dual synchronous step-down controller with adjustable LDO

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Design guidelines

PM6681A

36/47

Equation 27

Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:

Equation 28

Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.

If the ripple is very small (lower than approximately 30 mV), a further compensation network,

named virtual ESR network, is needed. This additional part generates a triangular ripple

that is added to the ESR output voltage ripple at the input of the integrator network. The

complete control schematic is represented in Figure 40.

Figure 40.

Virtual ESR network

The T node voltage is the sum of the output voltage and the triangular waveform generated

by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent

ESR RESR.

A good trade-off is to design the network in order to achieve an RESR given by:

Equation 29

filt

INT

filt

INT

CUT

INT

RIPPLEout

filt

INT

RIPPLEout

RIPPLEINT

out

RIPPLE

ESR

−

∆

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