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M48T35-70PC1TR bảng dữ liệu(PDF) 9 Page - STMicroelectronics |
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M48T35-70PC1TR bảng dữ liệu(HTML) 9 Page - STMicroelectronics |
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9 / 29 page ![]() M48T35 M48T35Y Operation modes 9/29 If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 5. Read mode AC waveforms Note: WRITE Enable (W) = High. Table 3. Read mode AC characteristics 2.2 Write mode The M48T35/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE Cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during Symbol Parameter(1) 1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). M48T35/Y Unit Min Max tAVAV READ Cycle Time 70 ns tAVQV Address Valid to Output Valid 70 ns tELQV Chip Enable Low to Output Valid 70 ns tGLQV Output Enable Low to Output Valid 35 ns tELQX (2) 2. CL = 5pF. Chip Enable Low to Output Transition 5 ns tGLQX (2) Output Enable Low to Output Transition 5 ns tEHQZ (2) Chip Enable High to Output Hi-Z 25 ns tGHQZ (2) Output Enable High to Output Hi-Z 25 ns tAXQX Address Transition to Output Transition 10 ns AI00925 tAVAV tAVQV tAXQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ VALID A0-A14 E G DQ0-DQ7 VALID |
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