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L6911E bảng dữ liệu(PDF) 18 Page - STMicroelectronics

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Device description
L6911E
18/34
5.8
Input capacitor
The input capacitor has to sustain the ripple current produced during the on time of the
upper MOS, so it must have a low ESR to minimize the losses.
The rms value of this ripple is:
Equation 11
Where D is the duty cycle. The equation reaches its maximum value with D = 0.5.
The losses in worst case are:
Equation 12
5.9
Compensation network design
The control loop is a voltage mode (Figure 9 on page 19) that uses a droop function to
satisfy the requirements for a VRM module, reducing the size and the cost of the output
capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load
transient, introducing a dependence of the output voltage on the load current: at light load
the output voltage will be higher than the nominal level, while at high load the output voltage
will be lower than the nominal value.
Figure 8.
Output transient response without (a) and with (b) the droop function
I
rms
I
OUT
D1
D
()
=
P
ESR I
rms
2
=



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