STM1403ASMQ6F datasheet(27/34 Pages) STMICROELECTRONICS

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STM1403

DC and AC parameters

27/35

Reset thresholds

VRST

(9)

Reset threshold

VCC falling

3.00

3.075

3.15

VCC rising

3.00

3.085

3.17

VCC falling

2.85

2.925

3.00

VCC rising

2.85

2.935

3.02

VCC falling

2.55

2.625

2.70

VCC rising

2.55

2.635

2.72

trec

RST pulse width

140

200

280

Push-button reset input

tMLMH

tMR

MR pulse width

100

tMLRL

tMRD

MR to RST output delay

500

Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VRST (max) to 3.6 V; and VBAT = 2.8 V (except where

noted); typical values are for 3.3 V and 25°C.

VCC supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at

VBAT = 3.6 V, and VCC = 3.6 V. The state of RST and PFO is tested at VCC = VCC (min). VBAT is voltage measured at the

pin.

Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V.

Guaranteed by design.

The leakage current measured on the RST, SAL, PFO, and BLD pins are tested with the output not asserted (output high

impedance).

When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.

When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.

Maximum external capacitive load on VREF pin cannot exceed 1nF.

The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents

internal oscillation.

Table 6.

DC and AC characteristics (continued)

Sym

Alter-

native

Description

Test condition(1)

Min

Typ

Max

Unit

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