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USBUF01P6 bảng dữ liệu(PDF) 6 Page - STMicroelectronics |
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USBUF01P6 bảng dữ liệu(HTML) 6 Page - STMicroelectronics |
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6 / 9 page ![]() Technical information USBUF01P6 6/9 This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due the low current involved after the resistance Rt. The measurements done hereafter show very clearly (Figure 7.a) the high efficiency of the ESD protection: – no influence of the parasitic inductances on Voutput stage –Voutput clamping voltage very close to VBR (breakdown voltage) in the positive way and -VF (forward voltage) in the negative way Figure 7. Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge. Please note that the USBUF01P6 is not only acting for positive ESD surges but also for negative ones. For these kinds of disturbances it clamps close to ground voltage as shown in Figure 7.b. a: Positive surge b: Negative surge |
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