STLVD111 datasheet(4/12 Pages) STMICROELECTRONICS

4 / 12 page

STLVD111

4/12

DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise

specified (Note 1, 2)

NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground

unless otherwise specified.

NOTE 2: All typical values are given for VCC =2.5V and TA = 25°C unless otherwise stated.

LVDS TIMING CHARACTERISTICS (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise specified

(Note 4)

NOTE 4: Generator waveforms for all test conditions: f=1MHz, ZO =50 Ω (unless otherwise specified).

CONTROL REGISTER TIMING CHARACTERISTICS (TA =-40 to 85 °C, VCC = 2.5V ± 5%, EN=H, unless

otherwise specified (Figure 4)

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

VBB

Output Reference Voltage

VCC = 2.5 V

1.15

1.25

1.35

ICCD

Power Supply Current

All driver enabled and loaded

125

160

CIN

Input Capacitance

VI =0V toVCC

5pF

COUT

Output Capacitance

VIH

Logic Input High Threshold

VCC = 2.5 V

VIL

Logic Input Low Threshold

VCC = 2.5 V

0.8

Logic Input Current

VCC = 2.5 V, VIN =VCC or GND

±10

µA

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

tTLH, tTHL Transition Time

RL = 100 Ω,CL = 5 pF, Fig. 5, 6)

220

300

tPHL, tPLH Propagation Delay Time

(Fig. 5, 6)

2.5

fMAX

Maximum Input Frequency

700

900

MHz

tSKEW

Bank Skew

(Fig. 1)

Part to Part Skew

(Fig. 2)

100

Pulse Skew

(Fig. 3)

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

fMAX

Maximum Frequency of Shift

(Fig. 7)

100

150

MHz

Clock to SI Setup Time

(Fig. 7)

Clock to SI Hold Time

(Fig. 7)

1.5

trem

Enable to Clock Removal Time

(Fig. 7)

1.5

Minimum Clock Pulse Width

(Fig. 7)

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