STLC5445

16/23

tioned delaying function requires, for each of the four channels, one Capacitor of 100nF has to

be connected between each CODCn and ground.

OPERATIVE DESCRIPTION

The device comprises three main blocks: the Analog section , the Logic section and the Relay driver section.

The Analog section feeds the four lines and detects their status.

The Logic section allows to exchange information and commands between the QLFC and the external digital

system.

The Relay driver section is completely independent: each relay command input is related to its own driver with-

out any conditioning.

Analog Section (see the Block diagram at page 3)

The ANALOG section comprises the Channel 0-Channel 3 block, the Reference & biasing generation block

and the Thermal monitoring block.

As shown in the channel's card of the block diagram, the WBn and WAn pins to which the line is connected are

respectively routed to the battery ground and to the VBAT line: WBn goes to BGND through the upper side sens-

ing resistor; WAn goes to VBAT through a power DMOS and the lower side sensing resistor. The ON/OFF con-

trol for the power DMOS comes from the outside world through the Logic interface block.

The implemented topology for the circuit used to cancel the longitudinal current effect is a DC coupled topology:

it doesn't need external capacitors and its frequency band starts from DC.

The QLFC has a double protection provided by its current limiting and thermal monitoring capabilities.

The current limit threshold (ILIMT) of the four channels is hardware programmable by means of a single, exter-

nal resistor (RLIM):

.

The protection implemented by the thermal monitoring is based on a three levels control system:

A first temperature threshold controls the Power on sequencer (see the Logic Section for a de-

tailed description of its behaviour). When activated (PBIT pin Low), the Power on sequencer

manages the channels' activation requests received through the Parallel (PSC pin Low) or the

MPI (PSC pin High) interface. The incoming channels' activation requests are stored in the

Power on sequencer and then satisfied, one at a time, only when the previously activated chan-

nel leaves the current limiting condition that normally occurs at power on, due to the capacitive

element that is part of the ISDN load. However when the chip's internal temperature reaches

110°C, only the already stored activation requests will be satisfied; the new, eventually incom-

ing ones, will be rejected and will be processed when the internal temperature decreases down

to 100°C.

A second temperature threshold is set at 130°C. When this value is reached the channels that

are in current limiting condition are switched off and their reactivation will only be possible when

the chip's internal temperature has decreased down to 120°C or, if the Power on sequencer is

activated, down to 100°C.

The third temperature threshold is set at 160°C. When this temperature is reached the activated

channels will all be switched off and their reactivation will only be possible when the chip's in-

ternal temperature has decreased down to 150°C. The user must however take into account

that if (like in ISDN application) the load seen by the channel has a high capacitive component,

at channel's turn on a current limiting condition will always occur and the eventually reactivated

channels will almost instantaneously be switched off by the 130°C monitoring circuit, if the

chip's internal temperature is still higher than 120°C. More over (as explained at the previous

point) if the Power on sequencer is activated it will not be possible to switch on any channel until

the chip has cooled down to 100°C.

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LIMIT

1.236 2155

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R

LIM

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