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STLC5432 bảng dữ liệu(PDF) 19 Page - STMicroelectronics

tên linh kiện STLC5432
Giải thích chi tiết về linh kiện  2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
PDF  46 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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STLC5432 bảng dữ liệu(HTML) 19 Page - STMicroelectronics

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DELAY BETWEEN INPUT SIGNAL (LI1 OR LI2) AND OUTPUT SIGNAL (LCR) AT 8KHz AFTER
SYNCHRONIZING (when SLCR = 1, LP4R Register Bit)
LP4
Loopback 4
When this bit is at ”1”, loop back 4 is
validated during Time Slot selected. The
loop back is located between DOUT and
DIN pins. The loop back is transparent
during the Time Slot selected. DOUT
always delivers the contents of each Time
Slot.
SLCR Synchronization of Low Clock Received
Relevant if LTM (CR1) = 0.
SLCR = 1, LCR output signal will be syn-
chronized once when MFR bit (or MFNR
bit) will go to ”1”. After synchronizing, the
falling edge of LCR signal is in accord-
ance with the 6th bit of time slot 1 seen
at the input of the circuit. (LI1 pin or LI2
pin). The input signal is assumed without
jitter.
SLCR = 0, LCR output signal is free. The
LCR frequency is a submultiple of HCR
frequency.
STLC5432
19/46



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