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TSH70CDT bảng dữ liệu(PDF) 21 Page - STMicroelectronics |
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TSH70CDT bảng dữ liệu(HTML) 21 Page - STMicroelectronics |
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21 / 33 page ![]() TSH70,71,72,73,74,75 Testing Conditions 21/33 5 Testing Conditions 5.1 Layout precautions To use the TSH7X circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: – First of all, the implementation of a proper ground plane in both sides of the PCB is mandatory for high speed circuit applications to provide low inductance and low resistance common return. – Power supply bypass capacitors (4.7uF and ceramic 100pF) should be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. The power supply capacitors must be incorporated for both the negative and the positive pins. ● Proper termination of all inputs and outputs must be in accordance with output termination resistors; in this way, the amplifier load will be resistive only, and the stability of the amplifier will be improved. ● All leads must be wide and as short as possible (especially for op-amp inputs and outputs) in order to decrease parasitic capacitance and inductance. ● For lower gain applications, care should be taken to avoid large feedback resistance (>1k Ω) in order to reduce the time constant of parasitic capacitances. ● Choose component sizes as small as possible (SMD). ● Finally, on output, the load capacitance must be negligible to maintain good stability. You can put a serial resistance as close as possible to the output pin to minimize capacitance. 5.2 Maximum input level Figure 47. CCIR330 video line The input level must not exceed the following values: ● negative peak: must be greater than -VCC+400mV. ● positive peak value: must be lower than +VCC-400mV. |
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