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3.8 TIMING

Table 17. describes the timing relationships between important signals.

3.9 POWER UP RESET

When the voltage on the RESETN pin is low the bits in the control register will be reset as per the detailed reg-

ister maps in “Digital Interface And Memory Map” on page 20.

In addition, digital output pins, DTX, FRMCLK, and RXSOUT[1:0] are high impedance. The other digital outputs

are always as defined in Table 1 on page 2.

Table 17. Timing

Symbol

Parameter

Spec

Min

<1>Load on all output pads assumed to be < 25pF.This gives a delay through the TLCHT pad of approximately 5ns.

Spec

Max

Unit

s

ENB falling to DIGCLK rising

1

5

ns

ENB rising to DIGCLK falling

1

5

ns

Data in valid to DIGCLK falling

2

5

ns

DIGCLK falling to Data in hold

2

5

ns

DIGCLK rising to Data out valid

5

10

ns

TXSIN[1:0] valid to CK35M falling

2

5

ns

CK35M falling to TXSIN[1:0] hold

2

5

ns

CK35M rising to RXSOUT[1:0] valid

5

10

ns

CK35M rising to FRMCLK valid

5

10

ns

DIGREF rising to CK35M rising

10

12

20

ns

DIGREF rise time (20% to 80%)

1

2

3

ns

DIGREF fall time (80% to 20%)

1

2

3

ns