ST8024CTR datasheet(17/31 Pages) STMICROELECTRONICS

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ST8024

Functional description

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Figure 4.

Voltage supervisor

5.2.2

With an external divider on pin PORADJ

If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Figure 1), then the

following occurs:

– The internal threshold voltage Vth2 is overridden by the external voltage and by the

hysteresis, therefore:

Vth2(ext)(rise) = (1 + R1/R2) x (Vbridge + Vhys(ext)/2)

Vth2(ext)(fall) = (1 + R1/R2) x (Vbridge - Vhys(ext)/2)

where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.

– The reset pulse width tW is doubled to approximately 16 ms.

Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed

when the voltage on pin PORADJ exceeds 1 V.

This ensures that after detection of the external bridge by the IC during power-on, the input

current on pin PORADJ does not cause inaccuracy of the bridge voltage.

The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage

may be up to VDD.

5.2.3

Application examples

The voltage supervisor is used as power-on reset and as supply dropout detection during a

card session. Supply dropout detection is to ensure that a proper deactivation sequence is

followed before the voltage is too low. For the internal voltage supervisor to function, the

system microcontroller should operate down to 2.35 V to ensure a proper deactivation

sequence. If this is not possible, external resistor values can be chosen to overcome the

problem.

5.3

Clock circuitry

The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a

crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2.

The clock frequency can be fXTAL, 1/2 x fXTAL, 1/4 x fXTAL or 1/8 x fXTAL. Frequency selection

is made via inputs CLKDIV1 and CLKDIV2 (see Table 21).

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