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M41T82 bảng dữ liệu(PDF) 43 Page - STMicroelectronics

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M41T82 bảng dữ liệu(HTML) 43 Page - STMicroelectronics

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M41T82 M41T83
Clock operation
43/58
3.16
OTP bit operation (M41T83 in SOX18 package only)
When the OTP (One Time Programmable) bit is set to a '1,' the value in the internal OTP
registers will be transferred to the analog calibration register (12h) and are “Read only.” The
OTP value is programmed by the manufacturer, and will contain the calibration value
necessary to achieve ±5 ppm at room temperature after two SMT reflows. This clock
accuracy can then be guaranteed to drift no more than ±3 ppm the first year, and ±1 ppm for
each following year due to crystal aging.
If the OTP bit is set to '0,' the analog calibration register will become a WRITE/READ
register and function like standard SRAM memory cells, allowing the user to implement any
desired value of analog calibration.
When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog
registers transfer the value from the OTP to the analog registers due to the OTP Read
operation.
Table 16.
Initial power-up default values (part 2)
Condition(1)
1.
All other control bits power-up in an undetermined state.
RPT11-15
HT
OF
TE
TI/TP
(2)
2.
M41T83 only.
TIE
(2)
TD1 TD0 RS0 RS1-3
OTP
(2)
A2IE
(2)
RPT21-
25
AL2E
Initial
Power-up
01
1
0
0
0
1
1
1
0
0
0
0
0
Subsequent
Power-up(3) (4)
3.
With battery back-up.
4.
UC = unchanged.
UC
1
UC
0
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC



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