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M41ST85WMH6F bảng dữ liệu(PDF) 28 Page - STMicroelectronics |
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M41ST85WMH6F bảng dữ liệu(HTML) 28 Page - STMicroelectronics |
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28 / 41 page ![]() Clock operation M41ST85W 28/41 3.13 trec bit Bit D7 of Clock Register 04h contains the trec Bit (TR). trec refers to the automatic continuation of the deselect time after VCC reaches VPFD. This allows for a voltage settling time before WRITEs may again be performed to the device after a power-down condition. The trec Bit will allow the user to set the length of this deselect time as defined by Table 6. 3.14 Initial power-on defaults Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog Register, FT, AFE, ABE, SQWE, and TR. The following bits are set to a '1' state: ST, OUT, and HT (see Table 7). Table 6. trec definitions Table 7. Default values trec bit (TR) STOP bit (ST) trec time Units Min Max 00 96 98 ms 01 40 200(1) 1. Default Setting ms 1 X 50 2000 µs Condition TR ST HT Out FT AFE ABE SQWE Watchdog register(1) 1. WDS, BMB0-BMB4, RB0, RB1. Initial Power-up(2) 2. State of other control bits undefined. 011 10 00 0 0 Subsequent Power-up (with battery back-up)(3) 3. UC = Unchanged UC UC 1 UC 0 0 0 0 0 |
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