MOSEL VITELIC

V61C51161024

7

V61C51161024 Rev. 1.0 July 1998

Switching Waveforms (Write Cycle)

NOTES:

1.

The internal write time of the memory is defined by the overlap of CE active and WE low. All signals must be active to initiate and

any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second

transition edge of the signal that terminates the write.

2.

3.

During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

4.

5.

If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must

not be applied to them.

6.

ADDRESS

OUTPUT

INPUT

CE

WE

51161024-10

(6)

(2)

(3)

(1)

UBE, LBE

ADDRESS

OUTPUT

INPUT

CE

WE

UBE, LBE

51161024-11

(2)

Hi-Z

(5)

(6)