T84C5112-RKFIL datasheet(14/97 Pages) ATMEL

14 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

CKCON0 - Clock Control Register (8Fh)

Reset Value = X000 0000b

Not bit addressable

Table 3. CKCON1 Register

CKCON1 - Clock Control Register

Reset Value = XXXX XX00b

Not bit addressable

WdX2

PcaX2

SiX2

T1X2

T0X2

Bit

Number

Bit

Mnemonic

Description

Reserved

WdX2

Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

PcaX2

Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is

low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

SiX2

Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is

low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reserved

T1X2

Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

T0X2

Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.

Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.

BRGX2

SPIX2

Bit

Number

Bit

Mnemonic

Description

Reserved

SPIX2

SPI clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

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