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XC2000 bảng dữ liệu(PDF) 30 Page - Infineon Technologies AG |
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XC2000 bảng dữ liệu(HTML) 30 Page - Infineon Technologies AG |
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30 / 647 page  XC2000 Derivatives System Units (Vol. 1 of 2) Architectural Overview Preliminary User’s Manual 2-2 V1.0, 2007-06 ArchitectureX2K, V1.0 2.1 Basic CPU Concepts and Optimizations The main core of the CPU consists of a set of optimized functional units including the instruction fetch/processing pipelines, a 16-bit Arithmetic and Logic Unit (ALU), a 40-bit Multiply and Accumulate Unit (MAC), an Address and Data Unit (ADU), an Instruction Fetch Unit (IFU), a Register File (RF), and dedicated Special Function Registers (SFRs). Single clock cycle execution of instructions results in superior CPU performance, while maintaining C166 code compatibility. Impressive DSP performance, concurrent access to different kinds of memories and peripherals boost the overall system performance. Figure 2-2 CPU Block Diagram DPRAM CPU IPIP RF R0 R1 GPRs R14 R15 R0 R1 GPRs R14 R15 IFU Injection/ Exception Handler ADU MAC mca04917_x.vsd CPUCON1 CPUCON2 CSP IP Return Stack FIFO Branch Unit Prefetch Unit VECSEG TFR +/- IDX0 IDX1 QX0 QX1 QR0 QR1 DPP0 DPP1 DPP2 DPP3 SPSEG SP STKOV STKUN +/- MRW MCW MSW MAL +/- MAH Multiply Unit ALU Division Unit Multiply Unit Bit-Mask-Gen. Barrel-Shifter +/- MDC PSW MDH ZEROS MDL ONES R0 R1 GPRs R14 R15 CP WB Buffer 2-Stage Prefetch Pipeline 5-Stage Pipeline R0 R1 GPRs R14 R15 PMU DMU DSRAM EBC Peripherals PSRAM Flash/ROM |
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