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STE100 bảng dữ liệu(PDF) 48 Page - STMicroelectronics

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STE100 bảng dữ liệu(HTML) 48 Page - STMicroelectronics

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6.4 Receive scheme and Receive early interrupt scheme
The following figure shows the difference of timing without early interrupt and with early interrupt.
Figure 12. Receive data flow (without early interrupt and with early interrupt)
Figure 13. Detailed Receive Early interrupt flow
: with early interrupt
: without early interrupt
incoming packet
receive FIFO operation
FIFO-to-host memory operation
interrupt
driver read header
higher layer process
driver read the rest data
time
receive early interrupt
driver read header(early)
higher layer process(early)
driver read the rest data
finish time
finish time
FIFO-to-host memory
i
time
receive early
driver read
higher layer
driver read the rest
finish
i
1
st
descriptor
full
2
nd descriptor
The size of 1
st
descriptor is
programmed as the
header size in
advance
issue 2
nd
interrupt at end
of packet



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