DS5000FP datasheet(5/22 Pages) DALLAS

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DS5000FP

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DESCRIPTION

11, 9, 7, 5,

1, 79, 77,

P0.0-P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a logic 1.

It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus.

When used in this mode, it does not require pullups.

13, 14

VCC - +5V

16, 8, 18,

80, 76, 4,

6, 20, 24,

26, 28, 30,

33, 35, 37

BA14-0. Byte-wide Address bus bits 14-0. This 15 bit bus is combined with the non-

multiplexed data bus (BD7-0) to access NV SRAM. Decoding is performed on CE1 and

CE2

. Read/write access is controlled by R/ W . BA14-0 connect directly to an 8k or 32k

SRAM. If an 8k RAM is used, BA13 and BA14 will be unconnected. Note BA13 and

BA14 are inverted from the true logical address. Also note that BA14 is lithium backed.

71, 69, 67,

65, 61, 59,

57, 55

BD7-0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the

non-multiplexed address bus (BA14-0) to access NV SRAM. Decoding is performed on

CE1

and CE2 . Read/write access is controlled by R/W. BD7-0 connect directly to an 8k

or 32k SRAM, and optionally to a Real-time Clock.

R/W - Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide

bus. It is controlled by the memory map and Partition. The blocks selected as Program

(ROM) will be write protected.

CE1

- Chip Enable 1. This is the primary decoded chip enable for memory access on the

Byte-wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium backed.

It will remain in a logic high inactive state when VCC falls below VLI.

CE2

- Chip Enable 2. This chip enable is provided to bank switch to a second block of

32k bytes of nonvolatile data memory. It connects to the chip enable input of one SRAM

or one lithium-backed peripheral such a DS1283 clock. CE2 is lithium backed. It will

remain in a logic high inactive state when VCC falls below VLI.

VCCO - VCC Output. This is switched between VCC and VLI by internal circuits based on

the level of VCC. When power is above the lithium input, power will be drawn from VCC.

The lithium cell remains isolated from a load. When VCC is below VLI, the VCCO switches

to the VLI source. VCCO is connected to the VCC pin of an SRAM.

VLIL - Lithium Voltage Input. Connect to a lithium cell greater than VLImin and no greater

than VLImax as shown in the electrical specifications. Nominal value is +3V.

2, 3, 22,

23, 32, 42,

43, 62, 63,

NC do not connect.

INSTRUCTION SET

The DS5000FP executes an instruction set that is object code compatible with the industry standard 8051

microcontroller. As a result, software development packages such as assemblers and compilers that have

been written for the 8051 are compatible with the DS5000FP. A complete description of the instruction

set and operation are provided in the User’s Guide section of the Secure Microcontroller Data Book.

Also note that the DS5000FP is embodied in the DS5000(T) and DS2250(T) modules. The DS5000(T)

combines the DS5000FP with one SRAM of either 8 or 32 kbytes and a lithium cell. An optional Real

Time Clock is also available in the DS5000T. This is packaged in a 40-pin DIP module. The DS2250(T)

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