T84C5112-RKFIV datasheet(46/97 Pages) ATMEL

46 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Figure 21. SPI Interrupt Requests Generation

12.4.5. Registers

There are three registers in the module that provide control, status and data storage functions. These registers are

describes in the following paragraphs.

12.4.5.1. Serial Peripheral CONtrol register (SPCON)

The Serial Peripheral Control Register does the following:

Selects one of the Master clock rates,

Configure the SPI module as Master or Slave,

Selects serial clock polarity and phase,

Enables the SPI module,

Frees the SS pin for a general purpose

Table 23 describes this register and explains the use of each bit:

Table 23. Serial Peripheral Control Register

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

Number

Bit Mnemonic

R/W

Mode

Description

SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate

SPEN

Serial Peripheral Enable

Clear to disable the SPI interface

Set to enable the SPI interface

SSDIS

SS Disable

Clear to enable SS# in both Master and Slave modes

Set to disable SS# in both Master and Slave modes. In Slave mode, this bit has no effect if

CPHA = Õ0Õ

MSTR

Serial Peripheral Master

Clear to configure the SPI as a Slave

Set to configure the SPI as a Master

CPOL

Clock Polarity

Clear to have the SCK set to Õ0Õ in idle state

Set to have the SCK set to Õ1Õ in idle low

CPHA

Clock Phase

Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL)

Set to have the data sampled when the SPSCK returns to idle state (see CPOL)

SSDIS

MODF

CPU Interrupt Request

SPI Receiver/error

CPU Interrupt Request

SPI Transmitter

SPI

CPU Interrupt Request

SPIF

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