C164CL datasheet(95/484 Pages) INFINEON

95 / 484 page

C164CI/C164SI

Derivatives

Interrupt and Trap Functions

User’s Manual

5-4

V3.1, 2002-02

Table 5-2 lists the vector locations for hardware traps and the corresponding status flags

in register TFR. It also lists the priorities of trap service for those cases in which more

than one trap condition might be detected within the same instruction. After any reset

(hardware reset, software reset instruction SRST, or reset by watchdog timer overflow)

program execution starts at the reset vector at location 00’0000H. Reset conditions have

priority over every other system activity and, therefore, have the highest priority (trap

priority III).

Software traps may be initiated to any vector location between 00’0000H and 00’01FCH.

A service routine entered via a software TRAP instruction is always executed on the

current CPU priority level which is indicated in bit field ILVL in register PSW. This means

that routines entered via the software TRAP instruction can be interrupted by all

hardware traps or higher level interrupt requests.

Table 5-2

Hardware Trap Summary

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Prio

Reset Functions

Hardware Reset

Software Reset

Watchdog Timer Overflow

–

RESET

00’0000H

00H

III

Class A Hardware Traps

Non-Maskable Interrupt

Stack Overflow

Stack Underflow

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008H

00’0010H

00’0018H

02H

04H

06H

Class B Hardware Traps

Undefined Opcode

Protected Instruction Fault

Illegal Word Operand Access

Illegal Instruction Access

Illegal External Bus Access

UNDOPC

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028H

0AH

Reserved

––

[2CH - 3CH][0BH - 0FH] –

Software Traps

TRAP Instruction

––

Any

[00’0000H -

00’01FCH]

in steps

of 4H

Any

[00H - 7FH]

Current

CPU

Priority

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