T89C51CC02CA-RATIM datasheet(122/145 Pages) ATMEL

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122

T89C51CC02

4126D–CAN–05/03

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register. This register also contains a global disable bit

which must be cleared to disable all the interrupts at the same time.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the

bit values and priority levels associated with each combination.

Table 102. Priority Level bit Values

A low-priority interrupt can be interrupted by a high priority interrupt but not by another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of the higher priority level is serviced. If interrupt requests of the same priority

level are received simultaneously, an internal polling sequence determines which

request is serviced. Thus within each priority level there is a second priority structure

determined by the polling sequence, See Table 103.

Table 103. Interrupt Priority Within Level

IPH.x

IPL.x

Interrupt Level Priority

0 (Lowest)

011

102

3 (Highest)

Interrupt Name

Interrupt Address Vector

Priority Number

External interrupt (INT0)

0003h

Timer0 (TF0)

000Bh

External interrupt (INT1)

0013h

Timer 1 (TF1)

001Bh

PCA (CF or CCFn)

0033h

UART (RI or TI)

0023h

Timer 2 (TF2)

002Bh

CAN (Txok, Rxok, Err or OvrBuf)

003Bh

ADC (ADCI)

0043h

CAN Timer Overflow (OVRTIM)

004Bh

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