T89C51CC02CA-RATIM datasheet(119/145 Pages) ATMEL

tên linh kiện	T89C51CC02CA-RATIM

Giải thích chi tiết về linh kiện	Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory

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119

T89C51CC02

4126D–CAN–05/03

Registers

Table 97. ADCF Register

ADCF (S:F6h)

ADC Configuration

Reset Value = 0000 0000b

Table 98. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset Value = X000 0000b

765

43210

CH 7

CH 6

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Bit

Number

Bit

Mnemonic

Description

7 - 0

CH 0:7

Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

765

43210

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from these bits are indeterminate. Do not set these bits.

PSIDLE

Pseudo Idle Mode (Best Precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

5ADEN

Enable/Standby Mode

Set to enable ADC

Clear for Standby mode.

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

ADSST

Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0

SCH2:0

Selection of Channel to Convert

See Table 96

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