AT80SND1C-ROTIL datasheet(149/210 Pages) ATMEL

149 / 210 page

149

AT8xC51SND1C

4109E–8051–06/03

Table 131. Serial Bit Rates

Notes:

1. These frequencies are achieved in X1 mode, F

PER = FOSC ÷ 2.

2. These frequencies are achieved in X2 mode, F

PER = FOSC.

Data Transfer

The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle

state(1) while the Clock Phase bit (CPHA in SPCON) defines the edges on which the

input data are sampled and the edges on which the output data are shifted (see

Figure 115 and Figure 116). The SI signal is output from the selected slave and the SO

signal is the output from the master. The AT8xC51SND1C captures data from the SI line

while the selected slave captures data from the SO line.

For simplicity, Figure 115 and Figure 116 depict the SPI waveforms in idealized form

and do not provide precise timing information. For timing parameters refer to the Section

“AC Characteristics”.

Note:

1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.

Figure 115. Data Transmission Format (CPHA = 0)

SPR2

SPR1

SPR0

Bit Rate (kHz) Vs F

PER

PER Divider

6 MHz

(1)

8 MHz

(1)

10 MHz

(1)

12 MHz

(2)

16 MHz

(2)

20 MHz

(2)

3000

4000

5000

6000

8000

10000

1500

2000

2500

3000

4000

5000

750

1000

1250

1500

2000

2500

375

500

625

750

1000

1250

187.5

250

312.5

375

500

625

93.75

125

156.25

187.5

250

312.5

46.875

62.5

78.125

93.75

125

156.25

128

6000

8000

10000

12000

16000

20000

MSB

bit 1

LSB

bit 2

bit 4

bit 3

bit 6

bit 5

bit 1

bit 2

bit 4

bit 3

bit 6

bit 5

MSB

LSB

MOSI (From Master)

MISO (From Slave)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

SS (to slave)

Capture point

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