AT87F55WD datasheet(3/26 Pages) ATMEL

3 / 26 page

AT87F55WD

The AT87F55WD provides the following standard features:

20K bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines,

three 16-bit timer/counters, a six-vector, two-level interrupt

architecture, a full-duplex serial port, on-chip oscillator, and

clock circuitry. In addition, the AT87F55WD is designed

with static logic for operation down to zero frequency and

supports two software selectable power saving modes. The

Idle Mod e st ops t he CPU wh ile allow ing th e RAM ,

timer/counters, serial port, and interrupt system to continue

functioning. The Power-down mode saves the RAM con-

tents but freezes the oscillator, disabling all other chip func-

tions until the next external interrupt or hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 can also be configured to be the multiplexed low-

order address/data bus during accesses to external

program and data memory. In this mode, P0 has internal

pullups.

Port 0 also receives the code bytes during QuickFlash pro-

gramming and outputs the code bytes during program veri-

fication. External pullups are required during program

verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (I

IL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), respectively, as

shown in the following table.

Port 1 also receives the low-order address bytes during

QuickFlash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (I

IL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application, Port 2 uses strong internal pul-

lups when emitting 1s. During accesses to external data

memory that use 8-bit addresses (MOVX @ RI), Port 2

emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during QuickFlash programming and verifi-

cation.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (I

IL) because of the pullups.

Port 3 also serves the functions of various special features

of the AT87F55WD, as shown in the following table.

Port 3 also receives some control signals for QuickFlash

programming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device. This pin drives

high for 96 oscillator periods after the Watchdog times out.

The DISRTO bit in SFR AUXR (address 8EH) can be used

to disable this feature. In the default state of bit DISTRO,

the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to external

Port Pin

Alternate Functions

P1.0

T2 (external count input to Timer/Counter 2),

clock-out

P1.1

T2EX (Timer/Counter 2 capture/reload trigger

and direction control)

Port Pin

Alternate Functions

P3.0

RXD (serial input port)

P3.1

TXD (serial output port)

P3.2

INT0 (external interrupt 0)

P3.3

INT1 (external interrupt 1)

P3.4

T0 (timer 0 external input)

P3.5

T1 (timer 1 external input)

P3.6

WR (external data memory write strobe)

P3.7

RD (external data memory read strobe)

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