AD8253ARMZ-R7 datasheet(16/24 Pages) AD

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AD8253

Rev. 0 | Page 16 of 24

THEORY OF OPERATION

10kΩ

REF

OUT

–IN

+IN

1.2kΩ

+VS

–VS

+VS

–VS

+VS

–VS

2.2kΩ

DGND

DIGITAL

GAIN

CONTROL

2.2kΩ

+VS

–VS

+VS

–VS

+VS

–VS

+VS

–VS

Figure 51. Simplified Schematic

Transparent Gain Mode

The AD8253 is a monolithic instrumentation amplifier based

on the classic 3-op-amp topology, as shown in Figure 51. It is

fabricated on the Analog Devices, Inc., proprietary iCMOS®

process that provides precision linear performance and a robust

digital interface. A parallel interface allows users to digitally

program gains of 1, 10, 100, and 1000. Gain control is achieved

by switching resistors in an internal precision resistor array (as

shown in Figure 51).

The easiest way to set the gain is to program it directly via a

logic high or logic low voltage applied to A0 and A1. Figure 52

shows an example of this gain setting method, referred to through-

out the data sheet as transparent gain mode. Tie WR to the

negative supply to engage transparent gain mode. In this mode,

any change in voltage applied to A0 and A1 from logic low to

logic high, or vice versa, immediately results in a gain change.

is the truth table for transparent gain mode, and

shows the AD8253 configured in transparent gain mode.

Table 5

Figure 52

All internal amplifiers employ distortion cancellation circuitry

and achieve high linearity and ultralow THD. Laser-trimmed

resistors allow for a maximum gain error of less than 0.03% for

G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout

optimized for high CMRR over frequency enables the AD8253

to offer a guaranteed minimum CMRR over frequency of 80 dB

at 20 kHz (G = 1). The balanced input reduces the parasitics

that in the past had adversely affected CMRR performance.

+15V

–15V

+IN

+5V

–IN

10μF0.1µF

G = 1000

DGND

REF

AD8253

NOTE:

1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −VS.

THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE

THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE

SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000.

GAIN SELECTION

This section describes how to configure the AD8253 for basic

operation. Logic low and logic high voltage limits are listed in

the Specifications section. Typically, logic low is 0 V and logic

high is 5 V; both voltages are measured with respect to DGND.

Refer to the specifications table (Table 2) for the permissible

voltage range of DGND. The gain of the AD8253 can be set

using two methods: transparent gain mode and latched gain

mode. Regardless of the mode, pull-up or pull-down resistors

should be used to provide a well-defined voltage at the A0 and

A1 pins.

Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000

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