AD2S1210DSTZ datasheet(23/36 Pages) AD

23 / 36 page

AD2S1210

Rev. 0 | Page 23 of 36

Address/Data Bit

The MSB of each 8-bit word written to the AD2S1210 indicates

whether the 8-bit word is a register address or data. The MSB

(D7) of each register address defined on the AD2S1210 is high.

The MSB of each data word written to the AD2S1210 is low.

Note that when a data word is written to the AD2S1210, the

MSB is internally reconfigured as a parity bit. When reading

data from any of the read/write registers (see Table 10), the

parity of Bit D6 to Bit D0 is recalculated and compared to the

previously stored parity bit. The MSB of the 8-bit output is used

to indicate whether a configuration error has occurred. If the

MSB is returned high, this indicates that the data read back from

the device does not match the configuration data written to the

device in the previous write cycle.

Phase Lock Range

The phase lock range allows the AD2S1210 to compensate for

phase errors between the excitation frequency and the sine/cosine

inputs. The recommended mode of operation is to use the default

phase lock range of ±44°. If additional phase lock range is

required, a range of 360° can be set. However, in this mode of

operation, the AD2S1210 should be reset following a loss of

signal error. Failure to do so may result in a 180° error in the

angular output data.

Hysteresis

The AD2S1210 includes a hysteresis function, ±1 LSB, between

the output of the position integrator and the input to the position

to prevent flicker on the LSB. On the AD2S1210, the maximum

tracking rate is defined by the bandwidth. Each resolution setting

is internally configured with a different bandwidth, as outlined

in Table 1. The maximum tracking rate and the bandwidth are

inversely proportional to the resolution, that is, the maximum

tracking rate increases as the resolution is decreased. The option

of disabling the hysteresis allows the user to oversample the

position output and to achieve a higher resolution output within

the specified bandwidths through external averaging.

The hysteresis function can be enabled or disabled through

setting Bit D4 in the control register. Hysteresis is enabled by

default on power-up.

Set Encoder Resolution

The resolution of the encoder outputs of the AD2S1210 can be

set to the same resolution as the digital output or it can also be

set to a lower resolution. For example, when the resolution of

the AD2S1210 position outputs is set to 16 bits, the resolution

of the encoder outputs may be set to 14, 12, or 10 bits. This

allows the user to take advantage of the lower bandwidth and

improved performance of the 16-bit resolution setting without

requiring external divide down of the A-quad-B encoder outputs.

The default resolution of the encoder outputs on power-up is 16

bits. Refer to the Incremental Encoder Outputs section.

Table 23. Encoder Resolution Settings

EnRES0

EnRES1

Resolution (Bits)

Set Resolution

In normal mode, the resolution of the digital output is selected

using the RES0 and RES1 input pins (see Table 9). In

configuration mode, the resolution is selected by setting the

RES0 and RES1 bits in the control register. When switching

between normal mode and configuration mode, it is the

responsibility of the user to ensure that the resolution set in the

control register matches the resolution set by the RES0 and RES1

input pins. The default resolution of the digital output on power-

up is 12 bits.

SOFTWARE RESET REGISTER

Table 24. 8-Bit Register

Address

Bit

Read/Write

0xF0

D7 to D0

Write only

Addressing the software reset register, that is writing the 8-bit

address, 0xF0, of the software reset register to the AD2S1210

while in configuration mode, allows the user to initiate a soft-

ware reset of the AD2S1210. The software reset reinitializes the

excitation frequency outputs and the internal Type II tracking loop.

The data stored in the configuration registers is not overwritten

by a software reset. However, it should be noted that the data in

the fault register is reset. In an application that uses two or more

resolver-to-digital converters, which are both driven from the same

clock source, the software reset can be used to synchronize the

phase of the excitation frequencies across the converters.

FAULT REGISTER

Table 25. 8-Bit Register

Address

Bit

Read/Write

0xFF

D7 to D0

Read only

The AD2S1210 has the ability to detect eight separate fault condi-

tions. When a fault occurs, the DOS and/or the LOT output

pins are taken low. By reading the fault register, the user can

determine the cause of the triggering of the fault detection output

pins. Note that the fault register bits are active high, that is, the

fault bits are taken high to indicate that a fault has occurred.

Table 26. Fault Register Bit Descriptions

Bit

Description

Sine/cosine inputs clipped

Sine/cosine inputs below LOS threshold

Sine/cosine inputs exceed DOS overrange threshold

Sine/cosine inputs exceed DOS mismatch threshold

Tracking error exceeds LOT threshold

Velocity exceeds maximum tracking rate

Phase error exceeds phase lock range

Configuration parity error

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