EMC646SP16K

4Mx16 CellularRAM AD-MUX

49

Preliminary

Figure 36: Asynchronous WRITE Followed by Burst READ

Note:

1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency, latency code 2 (3 clocks),

WAIT active LOW, WAIT asserted during delay.

2. When the divice is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the

either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

CLK

ADV#

CE#

OE#

WAIT

A/DQ[15:0]

A[21:16]

UB#/LB#

WE#

Note 2

Valid Address

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid Address

Data

Valid Address

Valid Address

High-Z

Don’t Care

Undefined