Rev 0.6

EMLS232UA Series

512K x 32 x 4Banks Low Power SDRAM

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

NOTE :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the

next higher integer.

2. Minimum dealy is required to complete write.

3. Maximum burst refresh cycle: 8

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

Parameter

Symbol

Value

Unit

Note

Row active to row active delay

15

1

RAS to CAS delay

22.5

1

Row precharge time

22.5

1

Row active time

45

1

70,000

Row cycle time

67.5

1

Last data in to row precharge

15

2

Last data in to Active delay

-

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Auto refresh cycle time

80

3

Exit self refresh to active command

120

Col. address to col. address delay

1

CLK

4

Number of valid output data

CAS latency=3

2

ea

5

Number of valid output data

CAS latency=2

1

Number of valid output data

CAS latency=1

-