EM620FU16 Series

Low Power, 128Kx16 SRAM

8

merging Memory & Logic Solutions Inc.

merging Memory & Logic Solutions Inc.

Address

CS1

CS2

UB ,LB

WE

Data in

Data out

t

t

t

DW

t

DH

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)

High-Z

High-Z

Data Valid

NOTES (WRITE CYCLE)

goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double

measured from the beginning of write to the end of write.

or WE going high.