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ST92R195B bảng dữ liệu(PDF) 14 Page - STMicroelectronics

tên linh kiện ST92R195B
Giải thích chi tiết về linh kiện  ROMLESS HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
PDF  18 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92R195B bảng dữ liệu(HTML) 14 Page - STMicroelectronics

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ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
EXTERNAL MEMORY INTERFACE TIMING TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
TpC is the INTCLK clock period.
SPI TIMING TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; Cload= 50pF)
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(V
DD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified)
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields
Symbol
Parameter
Value
Unit
typ
max
TwDSR
DSN low level pulse width (read)
TpC*(1/2+WDS)-6
ns
TwDSW
DSN low level pulse width (write)
TpC*(1/2+WDS)-6
ns
TdDSR(DR)
DSN
↓ to data valid delay
TpC*(1/2+WDS)-16
ns
ThDR(DS)
Data to DSN
↑ hold time
0
ns
TdDS(A)
DSN
↑ to address active delay
TpC/2
ns
ThDS(AS)
DSN
↑ to ASN↓ delay
TpC/2 + 6
ns
TsRW(AS)
R/WN setup time before ASN
↑
TpC*(1/2 + WAS) - 8
ns
TdDSR(RW)
DSN
↑ to R/WN and address not valid delay
TpC/2
ns
TdDW(DSW)
Write data valid to DSN
↓ delay (write)
0
ns
ThDS(DW)
Data hold time after DSN
↑ (write)
TpC/2
ns
TdA(DR)
Address valid to data valid delay (read)
TpC*(3/2+WDS+WAS)-14
ns
Symbol
Parameter
Conditi on
Value
Unit
min
max
TsDI
Input Data Set-up Time
tbd
ns
ThDI
Input Data Hold Time
(1)
OSCIN/2 as internal Clock
1INTCLK
+100ns
ns
TdOV
SCK to Output Data Valid
tbd
ns
ThDO
Output Data Hold Time
tbd
ns
TwSKL
SCK Low Pulse Width
tbd
ns
TwSKH
SCK High Pulse Width
tbd
ns
Symbol
Parameter
Conditions
max
Value
Unit
Tjskw
Jitter on RGB output
36 MHz Skew corrector clock frequency
5*
ns



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