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ST7LITE02 bảng dữ liệu(PDF) 26 Page - STMicroelectronics

tên linh kiện ST7LITE02
Giải thích chi tiết về linh kiện  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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ST7LITE02 bảng dữ liệu(HTML) 26 Page - STMicroelectronics

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7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
s
External RESET source pulse
s
Internal LVD RESET (Low Voltage Detection)
s
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
s
Active Phase depending on the RESET source
s
256 CPU clock cycle delay
s
RESET vector fetch
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see
Figure 12).
Figure 14. RESET Sequence Phases
Figure 15. Reset Block Diagram
RESET
Active Phase
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
FILTER
1



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