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ST72E631K1M0 bảng dữ liệu(PDF) 78 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C
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ST72E631K1M0 bảng dữ liệu(HTML) 78 Page - STMicroelectronics

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I²C BUS INTERFACE (Cont’d)
5.7.5 Low Power Modes
5.7.6 Interrupts
Figure 41. Event Flags and Interrupt Generation
The I²C interrupt events are connected to the
same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC
register is reset (RIM instruction).
Mode
Description
WAIT
No effect on I²C interface.
I²C interrupts exit from Wait mode.
HALT
I²C registers are frozen.
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C
interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt
mode” capability.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
End of Byte Transfer Event
BTF
ITE
Yes
No
Address Matched Event (Slave mode)
ADSEL
Yes
No
Start Bit Generation Event (Master mode)
SB
Yes
No
Acknowledge Failure Event
AF
Yes
No
Stop Detection Event (Slave mode)
STOPF
Yes
No
Arbitration Lost Event (Multimaster configuration)
ARLO
Yes
No
Bus Error Event
BERR
Yes
No
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
EVF
INTERRUPT
ITE
*
* EVF can also be set by EV6 or an error from the SR2 register.



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