ST72411R datasheet(25/71 Pages) STMICROELECTRONICS

25 / 71 page

ST72411R

25/71

4.4 POWER SAVING MODES

4.4.1 Introduction

There are three Power Saving modes. Slow Mode

is selected by setting the relevant bits in the Mis-

cellaneous register. Wait and Halt modes may be

entered using the WFI and HALT instructions.

Table 5. Power Saving Modes

1 Except with external timer clock.

2 If the LVD bit in the MISCR register is reset

Note: To reduce power consumption (in Run or

Wait modes), the smartcard supply supervisor

(SSS) and the LCD can be disabled by software.

4.4.2 Slow Mode

In Slow mode, the oscillator frequency can be di-

vided by a value defined in the Miscellaneous

this lower frequency except the LCD driver and the

8-bit Timer which have a fixed clock. Slow mode is

used to reduce power consumption, and enables

the user to adapt the clock frequency to the avail-

able supply voltage.

4.4.3 Wait Mode

Wait mode places the MCU in a low power con-

sumption mode by stopping the CPU. The periph-

erals remain active. During Wait mode, the I bit

(CC Register) is cleared, so as to enable all inter-

rupts. All other registers and memory remain un-

changed. The MCU will remain in Wait mode until

an Interrupt or Reset occurs, the Program Counter

then branches to the starting address of the Inter-

rupt or Reset Service Routine.

The MCU will remain in Wait mode until a Reset or

an Interrupt occurs, causing it to wake up.

Refer to Figure 19.

Figure 19. Wait Mode Flow Chart

Mode

fCPU

CPU

Periph erals

switched off.

Wake up

Slow

fOSC/32 ON None

Wait

fOSC/2

fOSC/32

OFF None

- External I/O

- Timer

- LVDS (PDF Flag).

- Reset

Halt

OFF

- SSS

- TIMER 1

- LVDS

- LCD

- External I/O

- Timer

- Reset

WFI INSTRUCTION

RESET

INTERRUPT

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

CLEARED

OFF

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

SET

FETCH RESET VECTOR

OR SERVICE INTERRUPT

4096 CPU CLOCK

CYCLES DELAY

IF RESET

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

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