CAT5409WI-25 datasheet(8/16 Pages) CATALYST

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CAT5409

Doc. No. MD-2010 Rev. K

Characteristics subject to change without notice

INSTRUCTION AND REGISTER

DESCRIPTION

SLAVE ADDRESS BYTE

The first byte sent to the CAT5409 from the master/

processor is called the Slave/DPP Address Byte. The

most significant four bits of the Device Type address

are a device type identifier. These bits for the

CAT5409 are fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave

address and must match the physical device address

which is defined by the state of the A3 - A0 input pins

for the CAT5409 to successfully continue the

command sequence. Only the device which slave

address matches the incoming device address sent by

the master executes the instruction. The A3 - A0

inputs can be actively driven by CMOS input signals

or tied to VCC or VSS.

INSTRUCTION BYTE

The next byte sent to the CAT5409 contains the

instruction and register pointer information. The four

most significant bits used provide the instruction

opcode I [3:0]. The R1 and R0 bits point to one of the

four data registers of each associated potentiometer.

The least two significant bits point to one of four Wiper

Control Registers. The format is shown in Table 2.

Data Register Selection

Data Register Selected

DR0

DR1

DR2

DR3

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

(MSB)

(LSB)

WCR/Pot Selection

Instruction

Opcode

Data Register

Selection

ID3

ID2

ID1

ID0

0101

(MSB)

(LSB)

Device Type

Identifier

Slave Address

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