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ST5080A bảng dữ liệu(PDF) 6 Page - STMicroelectronics |
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ST5080A bảng dữ liệu(HTML) 6 Page - STMicroelectronics |
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6 / 32 page ![]() Following pin definitions are used only when COMBO I/II mode with separate MICROWIRE com- patible serial control port is selected. (MS input set equal one) PIN FUNCTIONS (continued) Pin Name Description 12 CO Control data Output: Serial control/status information is shifted out from the PIAFE on this pin when CS- is low on the falling odges of CCLK. 13 CI Control data Input: Serial Control information is shifted into the PIAFE on this pin when CS- is low on the rising edges of CCLK. 19 CCLK Control Clock input: This clock shifts serial control information into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 20 CS- Chip Select input: When this pin is low, control information is written into and out from the PIAFE via CI and CO pins. Following pin definitions are used only when the GCI mode is selected. (MS input set equal zero) PIN FUNCTIONS (continued) Pin Name Description 19,13,12,20 A0,A1,A2,A3 These pins select the address of PIAFE on GCI interface and must be hardwired to either VCC or GND. A0,A1,A2,A3 refer to C4,C5,C6,C7 bits of the first address byte respectively. ST5080A 6/32 |
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