Operation modes

M48T08, M48T08Y, M48T18

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Operation modes

As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock

oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are

interconnected at the upper eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.

The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour

BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are

made automatically. Byte 1FF8h is the clock control register. This byte controls user access

to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory

locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y

includes a clock control circuit which updates the clock bytes with current information once

per second. The information can be accessed by the user in the same manner as any other

location in the static memory array.

The M48T08/18/08Y also has its own Power-fail Detect circuit. The control circuitry

of tolerance, the circuit write protects the SRAM, providing a high degree of data security in

maintains data and clock operation until valid power returns.

Table 2.

Operating modes

Note:

Read mode

The M48T08/18/08Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip

Enable 1) is low, and E2 (Chip Enable 2) is high. The device architecture allows ripple-

through access of data from eight of 65,536 locations in the static storage array. Thus, the

unique address specified by the 13 address inputs defines which one of the 8,192 bytes of

data is to be accessed. Valid data will be available at the Data I/O pins within address

and G access times are also satisfied. If the E1, E2 and G access times are not met, valid

Mode

E1

E2

G

W

DQ0-DQ7

Power

Deselect

4.75 to 5.5V

or

4.5 to 5.5V

X

X

X

High Z

Standby

Deselect

X

X

X

High Z

Standby

WRITE

Active

READ

Active

READ

High Z

Active

Deselect

(1)

1.

See Table 11 on page 22 for details.

X

X

X

X

High Z

CMOS Standby

Deselect

XXX

X

High Z

Battery Back-up

Mode