AD7626 datasheet(9/11 Pages) AD

9 / 11 page

Preliminary Technical Data

AD7626

Rev. PrC | Page 9 of 11

THEORY OF OPERATION

Echoed-Clock Interface Mode

The AD7626 digital operation in “echoed-clock interface mode”

is shown in Figure 3. This interface mode, requiring just a shift

(FPGA, shift register, microprocessor, etc.). It requires 3 LVDS

pairs (D±, CLK±, and DCO±) between each AD7626 and the

digital host.

The clock DCO is a buffered copy of CLK and synchronous to

the data, D, which is updated on DCO+ falling edge (tD). By

keeping good propagation delay matching between D and DCO

through the board and the digital host, DCO can be can be used

to latch D with good timing margin for the shift register.

Conversions are initiated by a CNV pulse. The CNV must be

returned low ≤ tCNVH(max) for valid operation. Once a

conversion has begun, it continues until completion. Additional

CNV pulses are ignored during the conversion phase. After the

time tMSB elapses, the host should begin to burst the CLK. Note

that tMSB is the maximum time for the MSB of the new

conversion result and should be used as the gating device for

CLK. The echoed clock, DCO, and data, D, will be driven in

phase with D being updated on the DCO+ falling edge and the

host should use the DCO+ rising edge to capture D. The only

requirement is that the 16 CLK pulses finish before the time

tCLKL elapses of the next conversion phase or the data will be lost.

From the time tCLKL to tMSB, D and DCO will be driven to 0’s.

CLK+

TCYC

CNV+

116

TCNVH

TCLKL

DCO+

116

D+

SAMPLE N

SAMPLE N+1

D-

D15

D14

CLK-

CNV-

DCO-

N-1

ACQUISITION

TACQ

TDCO

TCLK

TMSB

N-1

D15

N+1

D14

N+1

D13

N+1

TCLKD

Figure 3. Echoed-Clock Interface Mode Timing Diagram

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