SS1621
p. 4
Last update: 2008-06-03 04:36
PIN Description
PIN Name
I/O
Function
CS
I
Chip selection input with pull-high resistor
When the
CS is logic high, the data and command read from or written
to the SS1621 are disabled. The serial interface circuit is also reset. But
if
CS is at logic low level and is input to the CS pad, the data and com-
mand transmission between the host controller and the SS1621 are all
enabled.
RD
I
READ clock input with pull-high resistor
Data in the RAM of the SS1621 are clocked out on the falling edge of
the RD signal. The clocked out data will appear on the DATA line. The
host controller can use the next rising edge to latch the clocked out data.
WR
I
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the SS1621 on the rising edge of
the WR signal.
DATA
I/O
Serial data input/output with pull-high resistor
GND
—
Negative power supply, ground
OSCO
O
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order
to generate a system clock. If the system clock comes from an external
clock source, the external clock source should be connected to the OSCI
pad. But if and on-chip RC oscillator is selected instead, the OSCI and
OSCO pads can be left open.
VLCD
I
LCD power input
VDD
—
Positive power supply
IRQ
O
Time base or WDT overflow flag, NMOS open drain output
BZ, BZ
O
2kHz or 4kHz tone frequency output pair
COM0~COM3
O
LCD common outputs
SEG0~SEG31
O
LCD segment outputs
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