ST18952 datasheet(28/67 Pages) STMICROELECTRONICS

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ST18952

The current priority levels available are shown in below.

An interrupt request is acknowledged when its priority level (coded in the IPR register) is higher

than the current priority level. In this case, the current priority level becomes the interrupt

priority level and the previous current priority level is pushed onto the stack and displayed as

stack priority level (SPL)1.

The process is repeated over a range of four interrupt requests and the four previous current

stack priority levels are displayed on SPL1, SPL2, SPL3 and SPL4. If less than four interrupts

are pushed onto the stack, the unused SPL words are set to ‘000’. At the end of the interrupt

routine, the priority levels are popped from the stack.

The empty stack (ES) flag is used to indicate whether the stack is used or not. The ISP word

of the ISP register indicates the depth of the stack (see below).

Figure 8.2

ICR and ISPR Operation

Priority level

Coding

Acceptable IT level priority

- 1

111

0,1,2,3

000

1,2,3

001

2,3

010

011

Reserved

100 - 110

SPL4 SPL3 SPL2 SPL1 ES CPL

INTERRUPT LEVEL 2

PROGRAM

PROGRAM IT2

PROGRAM IT3

IT2

IT3

INTERRUPT LEVEL 3

-1

SPL4 SPL3 SPL2 SPL1 ES CPL

-1

SPL4 SPL3 SPL2 SPL1 ES CPL

-1

ISP

ICR

ISPR

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