STR730FZ1T7 datasheet(33/52 Pages) STMICROELECTRONICS

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STR73xFxx

Electrical parameters

33/52

PLL electrical characteristics

VDD = 5 V ± 10%, TA = -40° C to TAmax, unless otherwise specified

1. Flash memory programmed to enter Power Down mode during LPWFI.

Table 16.

PLL characteristics

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

fPLLIN

(1)

fPLLIN is obtained from fOSC directly or through an optional divider by 2.

Typical data are based on TA=25°C, VDD=5V

Max value is guaranteed by characterization, not tested in production.

PLL reference clock

FREF_RANGE = ‘0’

FREF_RANGE = ‘1’

1.5

3.0

5.0

MHz

fPLLOUT

PLL output clock

MX = ”00”

MX = ”01”

MX = ”10”

MX = ”11”

20 x fPLLIN

12 x fPLLIN

28 x fPLLIN

16 x fPLLIN

MHz

fMCLK

System clock

DX = 1..7

fPLLOUT/DX

MHz

fFREE

(2)

PLL free running

frequency

FREF_RANGE = ‘0’, MX0 = ’1’

FREF_RANGE = ‘0’, MX0 = ’0’

FREF_RANGE = ‘1’, MX0 = ’1’

FREF_RANGE = ‘1’, MX0 = ’0’

120

240

480

kHz

tLOCK

(3)

PLL lock time

Stable oscillator

(fPLLIN = 4 MHz), stable VDD

100

300

μs

Δt

PKJIT

PLL jitter (pk to pk)

fPLLIN = 4 MHz (pulse

generator)

1.5

Table 17.

Low-power mode wake-up timing

Symbol

Parameter

Conditions

Typ

Unit

tWUHALT

Wake-up from HALT mode

200

µs

tWUSTOP

Wake-up from STOP mode

RC high frequency in STOP mode

180

µs

RC low frequency in STOP mode

234

µs

tWULPWFI

Wake-up from LPWFI mode

Main voltage regulator on

RC oscillator off

fOSC = 4 MHz, fMCLK= fOSC/16

RAM or FLASH execution

µs

Main voltage regulator on

RC oscillator = high frequency

Flash execution

µs

Main voltage regulator on

RC oscillator = low frequency

Flash execution

3.6

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