TDA7333N datasheet(21/36 Pages) STMICROELECTRONICS

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TDA7333N

Functional description

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The meaning of each bit is described below:

3.8.1

rds_int register

rds_bd_ctrl[7:0]

read/write

frequency, quality sensitivity, demodulator pll settings

sinc4reg[7:0]

read/write

sinc4 filter settings (for internal use only)

testreg[7:0]

read/write

test modes (for internal use only)

pllreg4[7:0]

read/write

PLL control register 4

pllreg3[7:0]

read/write

PLL control register 3

pllreg2[7:0]

read/write

PLL control register 2

pllreg1[7:0]

read/write

PLL control register 1

pllreg0[7:0]

read/write

PLL control register 0

Table 7.

Registers description (continued)

Access

rights

Function

(1) If the interrupt source is changed form block A, B,

D, TA, TA EON to another one "no interrupt" must be

set before to clear the previous interrupt acknowledge.

Interrupt bit. It is set to one on every programmed interrupt. It is

reset by reading rds_int register. The inverted version is also

externally available on RDSINT pin.

itsrc[2:0] selects interrupt source (1).

Block A, B, D and TA, TA EON interrupts only if "synch" =1.

Synchronization information (refer to pages 13-15).

1: The module is already synchronized.

0: The module is synchronizing.

It is used to force a resynchronization. If it is set to one, the RDS

modules are forced to resynchronization state and the RAM buffer

address is reset.

This bit is reset automatically. It is read always as zero.

Buffer not empty.

1: At least one block is present in the RAM buffer.

0: The RAM buffer is empty.

rds_int, rds_bd_ctrl and pllreg4-0 write order.

This bit is only used in SPI mode and is read always as zero.

1: Update of rds_int, rds_bd_ctrl and pllreg4-0 with data shifted in.

0: No update of rds_int, rds_bd_ctrl and pllreg4-0.

bit name

access

bit 7

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

r/w

itsrc0

int

ar_res

bne

itsrc1

synch

write

reset value

itsrc2

(1)

itsrc2

itsrc1

interrupt source

itsrc0

buffer not empty

block B

block A

buffer full

block D

TA EON

no interrupt

rds_int

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